Table of Contents

Cover

Title Page

Copyright

Preface

Introduction

Digitally Controlled Switched-Mode Converters

System and Performance Gains via Digital Control

Chapter 1: Continuous-Time Averaged Modeling of DC–DC Converters

1.1 Pulse Width Modulated Converters

1.2 Converters in Steady State

1.3 Converter Dynamics and Control

1.4 State-Space Averaging

1.5 Design Examples

1.6 Duty Ratio d[k] Versus d(t)

1.7 Summary of Key Points

Chapter 2: The Digital Control Loop

2.1 Case Study: Digital Voltage-Mode Control

2.2 A/D Conversion

2.3 The Digital Compensator

2.4 Digital Pulse Width Modulation

2.5 Loop Delays

2.6 Use of Averaged Models in Digital Control Design

2.7 Summary of Key Points

Chapter 3: Discrete-Time Modeling

3.1 Discrete-Time Small-Signal Modeling

3.2 Discrete-Time Modeling Examples

3.3 Discrete-Time Modeling of Time-Invariant Topologies

3.4 Matlab® Discrete-Time Modeling of Basic Converters

3.5 Summary of Key Points

Chapter 4: Digital Control

4.1 System-Level Compensator Design

4.2 Design Examples

4.3 Other Converter Transfer Functions

4.4 Actuator Saturation and Integral Anti-Windup Provisions

4.5 Summary of Key Points

Chapter 5: Amplitude Quantization

5.1 System Quantizations

5.2 Steady-State Solution

5.3 No-Limit-Cycling Conditions

5.4 DPWM and A/D Implementation Techniques

5.5 Summary of Key Points

Chapter 6: Compensator Implementation

6.1 PID Compensator Realizations

6.2 Coefficient Scaling and Quantization

6.3 Voltage-Mode Control Example: Coefficients Quantization

6.4 Fixed-Point Controller Implementation

6.5 Voltage-Mode Converter Example: Fixed-Point Implementation

6.6 HDL Implementation of the Controller

6.7 Summary of Key Points

Chapter 7: Digital Autotuning

7.1 Introduction to Digital Autotuning

7.2 Programmable PID Structures

7.3 Autotuning via Injection of a Digital Perturbation

7.4 Digital Autotuning Based on Relay Feedback

7.5 Implementation Issues

7.6 Summary of Key Points

Appendix A: Discrete-Time Linear Systems and the Z-Transform

A.1 Difference Equations

A.2 Z-Transform

A.3 The Transfer Function

A.4 State-Space Representation

Appendix B: Fixed-Point Arithmetic and HDL Coding

B.1 Rounding Operation and Round-off Error

B.2 Floating-Point Versus Fixed-Point Arithmetic Systems

B.3 Binary Two's Complement (B2C) Fixed-Point Representation

B.4 Signal Notation

B.5 Manipulation of B2C Quantities and HDL Examples

Appendic C: Small-Signal Phase Lag of Uniformly Sampled Pulse Width Modulators

C.1 Trailing-Edge Modulators

C.2 Leading-Edge Modulators

C.3 Symmetrical Modulators

References

Index

IEEE Press Series on Power Engineering

End User License Agreement

Pages

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

277

278

279

280

281

282

283

284

285

286

287

288

289

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

Guide

Cover

Table of Contents

Preface

Begin Reading

List of Illustrations

Introduction

Figure 1 Digital controller architecture for high-frequency switched-mode power converters [13].

Figure 2 Digitally controlled point-of-load (POL) synchronous Buck dc–dc converter example. Analysis, modeling, design, and implementation of digital control loops are addressed in Chapters 1–6. An additional injection-based autotuning block is shown, which is further discussed in Chapter 7.

Figure 3 Experimental 0 to 8 A load step response in a digitally controlled POL Buck converter with conventional PID compensation [34] (f02-math-0015, 50mV/div; f02-math-0016, 5A/div; and timescale, 5 μ s/div). © 2009 IEEE.

Figure 4 Experimental 0A-8A step load response in a digitally controlled POL Buck converter with the time-optimal controller described in [34] (f02-math-0020: 50mV/div, f02-math-0021: 5A/div, timescale: 5 μ s/div). © 2009 IEEE.

Figure 5 Digitally controlled PWM converter with integrated frequency response measurement capabilities [80]. © 2008 IEEE.

Figure 6 Output voltage during system identification process in a 15- to 30-V Boost dc–dc converter operating at f02-math-0023 [80]. © 2008 IEEE.

Figure 7 Control-to-output magnitude and phase responses determined by the system identification process illustrated in Figure 5 and 6 [80]. © 2008 IEEE.

Chapter 1: Continuous-Time Averaged Modeling of DC–DC Converters

Figure 1.1 Pulse width modulated Boost converter.

Figure 1.2 (a) Converter waveforms with duty cycle modulation and (b) qualitative spectrum of a pulse width modulated signal.

Figure 1.3 Boost converter example.

Figure 1.4 Boost converter example: waveforms based on the small-ripple approximation.

Figure 1.5 Boost converter example: estimation of the ripple waveshapes.

Figure 1.6 Analog voltage-mode control of a synchronous Buck converter.

Figure 1.7 Typical analog control waveforms.

Figure 1.8 (a) Buck converter and its (b) averaged and (c) small-signal models.

Figure 1.9 Small-signal block diagram of the analog voltage-mode control.

Figure 1.10 Definition of the system loop gain c01-math-0144.

Figure 1.11 Averaged small-signal models of the (a) Buck, (b) Boost, and (c) Buck–Boost converters.

Figure 1.12 Synchronous Buck example: analog voltage-mode control scheme.

Figure 1.13 Synchronous Buck example: Bode plots of the uncompensated loop gain c01-math-0230.

Figure 1.14 Synchronous Buck example: Bode plots of the lead (PD) compensation transfer function.

Figure 1.15 Synchronous Buck converter example: Bode plots of the lead (PD) and PID compensation transfer functions.

Figure 1.16 Synchronous Buck example: Bode plots of the lead (PD), PID, and overall compensation transfer functions.

Figure 1.17 Synchronous Buck example: Bode plots of the theoretical and simulated system loop gain.

Figure 1.18 Synchronous Buck example: simulation of the system loop gain c01-math-0269.

Figure 1.19 Synchronous Buck example: 1.79 V c01-math-0280 1.8 V step reference responses.

Figure 1.20 Synchronous Buck example: 2.5 A c01-math-0281 5 A step load responses.

Figure 1.21 Synchronous Buck example: Bode plots of the open-loop and closed-loop output impedances.

Figure 1.22 Average current-mode control of a Boost converter.

Figure 1.23 Boost converter example: Bode plots of the control-to-inductor current transfer function.

Figure 1.24 Boost converter example: Bode plots of the compensator transfer function.

Figure 1.25 Boost converter example: Bode plots of the uncompensated and compensated current loop gains c01-math-0337 and c01-math-0338.

Figure 1.26 Boost converter example: 500 Wc01-math-0339250 W step-reference response.

Figure 1.27 Qualitative signal spectra in analog control.

Chapter 2: The Digital Control Loop

Figure 2.1 Digital voltage-mode control of a synchronous Buck converter.

Figure 2.2 (a) Block diagram of the A/D conversion process and (b) associated waveforms.

Figure 2.3 Sampling frequency higher than the switching frequency: (a) time-domain waveforms of the sensed signal before and after sampling and (b) qualitative signal spectra.

Figure 2.4 Sampling frequency equal to the switching frequency: (a) time-domain waveforms of the sensed signal before and after sampling and (b) qualitative signal spectra.

Figure 2.5 Example of dc aliasing in voltage sampling.

Figure 2.6 Commonly adopted PWM and sampling strategy for digital average current-mode control.

Figure 2.7 A/D converter quantization characteristic.

Figure 2.8 Timing diagram of the compensator operation.

Figure 2.9 Block diagram of a continuous-time PID compensator in the parallel (noninteracting) form.

Figure 2.10 Backward Euler approximation.

Figure 2.11 Block diagram of a discrete-time PID compensator obtained via backward Euler discretization of a continuous-time PID.

Figure 2.12 Tustin approximation.

Figure 2.13 Block diagram of a discrete-time PID compensator obtained via Tustin discretization of a continuous-time PID.

Figure 2.14 Comparison of Bode plots of the analog PID designed in Section 1.5.1 and its Tustin discretization.

Figure 2.15 (a) Block diagram of a counter-based digital pulse width modulator and (b) associated waveforms.

Figure 2.16 Duty cycle quantization operated by the DPWM.

Figure 2.17 Typical timing diagram of a hardware-based controller.

Figure 2.18 Typical timing diagram of a software-based controller.

Figure 2.19 Dirac approximation of the uniformly sampled pulse width modulator output.

Figure 2.20 Comparison between analog and digital control: steady-state output voltage waveform.

Figure 2.21 Comparison between analog and digital control: 1.79 Vc02-math-02061.8 V step-reference responses.

Figure 2.22 Comparison between analog and digital control: 2.5 Ac02-math-02075 A step-load responses.

Figure 2.23 Effect of the control delay: 1.79 Vc02-math-02161.8 V step reference responses.

Figure 2.24 Effect of the operating point on the modulation delay: comparison between (a) the 1.79 Vc02-math-02271.8 V and (b) the 3.29 Vc02-math-02283.3 V step-reference responses.

Figure 2.25 Qualitative spectra of (top) c02-math-0234 and c02-math-0235, (middle) the averaging operation, and (bottom) the baseband portions of c02-math-0236 and c02-math-0237.

Figure 2.26 Comparison between conventional and effective small-signal loop dynamics.

Chapter 3: Discrete-Time Modeling

Figure 3.1 (a) The switched inductor and (b) waveforms associated with its discrete-time model derivation.

Figure 3.2 Waveforms illustrating the discrete-time model derivation.

Figure 3.3 Synchronous Buck converter example: digital voltage-mode control.

Figure 3.4 Synchronous Buck converter example: timing diagram.

Figure 3.5 Synchronous Buck converter example: Bode plots of the control-to-output voltage transfer functions c03-math-0215 based on the discrete-time modeling approach and c03-math-0216 based on the standard averaged modeling approach.

Figure 3.6 Synchronous Buck converter example: a comparison between the discrete-time model c03-math-0226 and the effective c03-math-0227-domain model c03-math-0228 obtained by including the additional phase lag due to the total loop delay c03-math-0229.

Figure 3.7 Synchronous Buck converter example: comparison between Bode plots of the control-to-inductor current transfer functions c03-math-0241 based on continuous-time averaged model and c03-math-0242 based on the discrete-time model.

Figure 3.8 Effect of a static duty cycle perturbation on the inductor current sampled at the end of off-time interval.

Figure 3.9 Synchronous Buck converter example: comparison between the Bode plots of the discrete-time model c03-math-0271 and the effective c03-math-0272-domain model c03-math-0273.

Figure 3.10 Boost digital current-mode control.

Figure 3.11 Boost converter current-mode control example: timing diagram.

Figure 3.12 Boost converter example: Bode plots of the control-to-inductor current transfer functions c03-math-0286 based on the discrete-time model, and c03-math-0287 based on the averaged model.

Figure 3.13 Boost converter example: comparison between the discrete-time model c03-math-0301 and the effective c03-math-0302-domain model c03-math-0303.

Figure 3.14 Topological invariance of the Buck converter.

Figure 3.15 Small-signal discrete-time converter response to an input perturbation c03-math-0321.

Figure 3.16 Synchronous Buck converter example: Bode plots of c03-math-0468 calculated using the general discrete-time modeling approach and using the impulse-invariant discretization.

Figure 3.17 System template of the proposed Matlab® modeling framework.

Chapter 4: Digital Control

Figure 4.1 Definition of the c04-math-0006-domain loop gain c04-math-0007.

Figure 4.2 Bilinear mapping between the c04-math-0027-domain and the c04-math-0028-domain.

Figure 4.3 Block diagram of a digital PID compensator in the parallel form.

Figure 4.4 Asymptotic Bode plots of a digital PID in the c04-math-0106-domain.

Figure 4.5 Synchronous Buck converter example: Bode plots of the uncompensated loop gain c04-math-0150.

Figure 4.6 Synchronous Buck converter example: Bode plots of the compensator transfer function c04-math-0205: proportional-derivative (PD) part (dashed line) and the overall proportional-integral-derivative (PID) compensator (solid line).

Figure 4.7 Synchronous Buck converter example: Bode plots of the compensated voltage loop gain c04-math-0206 with proportional-derivative compensation (dashed line) and after the introduction of the integral term (solid line).

Figure 4.8 Synchronous Buck converter example: the setup for finding the c04-math-0207-domain loop gain c04-math-0208 by simulation, which emulates operation of a network analyzer.

Figure 4.9 Synchronous Buck converter example: 2.5 c04-math-02095 c04-math-0210 step-load response.

Figure 4.10 Synchronous Buck converter example: expanded view of the 2.5 Ac04-math-02115 A step-load response: (a) inductor current and (b) output voltage.

Figure 4.11 Boost digital current-mode control.

Figure 4.12 Boost converter example: Bode plots of the uncompensated loop gain c04-math-0233 and the loop gain c04-math-0234.

Figure 4.13 Boost converter example: 500 Wc04-math-0258250 W step reference response.

Figure 4.14 Digital multiloop control of a synchronous Buck converter.

Figure 4.15 Small-signal block diagram of the digital multiloop control.

Figure 4.16 Multiloop control example: Bode plots of the current loop gain.

Figure 4.17 Multiloop control example: Bode plots of the voltage loop gain.

Figure 4.18 Multiloop control example: closed-loop response to a 0 Ac04-math-03125 Ac04-math-03130 A step-load sequence.

Figure 4.19 Block diagram of a PFC system.

Figure 4.20 PFC main waveforms in steady state.

Figure 4.21 Digitally controlled Boost power factor corrector.

Figure 4.22 Boost PFC example: Bode plots of the current loop gain for three different c04-math-0389's.

Figure 4.23 Loss-free resistor as the core of the voltage loop dynamics.

Figure 4.24 Removal of the components of c04-math-0417 at the harmonics of the line frequency, by averaging over one-half of the line period c04-math-0418.

Figure 4.25 Model of the LFR output port averaged over one-half of the line period.

Figure 4.26 Qualitative spectra of (top) the PFC output voltage, (middle) its averaged version over half line period, and (bottom) the sampled PFC output voltage.

Figure 4.27 Boost PFC example: Bode plots of the uncompensated voltage loop gain c04-math-0451 for c04-math-0452, 250, and c04-math-0453.

Figure 4.28 Boost PFC example: Bode plots of the voltage loop gain c04-math-0454 for c04-math-0455, c04-math-0456, and c04-math-0457.

Figure 4.29 Boost PFC example: simulated 500 Wc04-math-0458250 W step load response.

Figure 4.30 Synchronous Buck example: Bode plots of the open-loop and closed-loop output impedances.

Figure 4.31 Synchronous Buck example: Bode plots of the open-loop and closed-loop audiosusceptibility.

Figure 4.32 Boost converter example: Bode plots of the open-loop and closed-loop input impedances.

Figure 4.33 Synchronous Buck example: impact of PWM saturation during a 0 Ac04-math-051010 c04-math-0511 step-load transient.

Figure 4.34 Saturated integrator.

Figure 4.35 Synchronous Buck example: effect of saturation of the integrator state variable.

Figure 4.36 Multiloop control example: saturation of the current loop setpoint and the control command.

Figure 4.37 Multiloop control example: effects of the saturation of the current loop setpoint without (“w/o AW”) and with anti-windup (“w AW”).

Figure 4.38 Anti-windup scheme based on conditional integration.

Chapter 5: Amplitude Quantization

Figure 5.1 Digital voltage-mode control of a synchronous Buck converter.

Figure 5.2 (a) A/D converter block diagram and (b) its quantization characteristic.

Figure 5.3 DPWM-induced quantization on the output voltage, Buck converter example.

Figure 5.4 DPWM-induced quantization on the output voltage, Boost converter example.

Figure 5.5 DC model of a digitally controlled converter, including A/D and DPWM quantization.

Figure 5.6 A graphical approach to finding a quiescent operating point in a digitally controlled converter with A/D converter and DPWM having very high resolutions. The expression for the sensed dc voltage c05-math-0073 as a function of the quantized value c05-math-0074 is shown for the synchronous Buck converter example.

Figure 5.7 A graphical approach to finding a quiescent operating point in a digitally controlled converter with A/D converter and DPWM having finite resolution. The expression for the sensed dc voltage c05-math-0088 as a function of the quantized value c05-math-0089 is shown for the synchronous Buck converter example.

Figure 5.8 DPWM resolution is coarser than the A/D resolution in terms of output voltage quantization.

Figure 5.9 DPWM resolution is finer than the A/D resolution in terms of output voltage quantization.

Figure 5.10 Simulated steady-state operation of the converter with a coarse DPWM resolution, so that the no-limit-cycling condition (5.22) is not met.

Figure 5.11 Simulated steady-state operation of the converter with a fine DPWM resolution, so that the no-limit-cycling condition (5.22) is met.

Figure 5.12 Waveforms illustrating quantization of the DPWM input signal c05-math-0145 due to A/D quantization and integral action of the digital compensator: (top) an impulse in error c05-math-0146 and (bottom) impulse response of an integral digital compensator with integral gain c05-math-0147.

Figure 5.13 Integral term resolution is coarser than the A/D resolution in terms of output voltage quantization.

Figure 5.14 Integral term resolution is finer than the A/D resolution in terms of output voltage quantization.

Figure 5.15 (a) Block diagram of a counter-based digital pulse width modulator and (b) associated waveforms.

Figure 5.16 Delay line DPWM: (a) architecture and (b) operating waveforms.

Figure 5.17 Hybrid DPWM: (a) architecture and (b) operating waveforms.

Figure 5.18 The control command c05-math-0207 in the hybrid DPWM of Figure 5.17.

Figure 5.19 c05-math-0239 modular placed in front of a hardware digital pulse width modulator.

Figure 5.20 Operating waveforms in the synchronous Buck converter example in Section 5.3.1 using 8-bit DPWM and a second-order c05-math-0256 modular to increase the effective resolution to 10 bits.

Figure 5.21 Windowed-flash A/D converter.

Chapter 6: Compensator Implementation

Figure 6.1 Effects of coefficient quantization on the system loop gain: adequate quantization (c06-math-0023), excessively coarse c06-math-0024 and c06-math-0025 quantization (c06-math-0026), and excessively coarse c06-math-0027 quantization (c06-math-0028).

Figure 6.2 Parallel realization of a digital PID compensator.

Figure 6.3 Direct realization of a digital PID compensator.

Figure 6.4 Cascade realization of a digital PID compensator.

Figure 6.5 Quantization/saturation block.

Figure 6.6 Coefficient scaling and quantization: (a) system-level view of the compensator as considered in the previous chapters and implementation-level view (b) before and (c) after coefficients quantization. Signals granularities are also indicated.

Figure 6.7 Maximum phase of c06-math-0142 at c06-math-0143.

Figure 6.8 Compensator relative sensitivity function c06-math-0192 (in %) at c06-math-0193 (parallel form).

Figure 6.9 Bode plots of c06-math-0194 and c06-math-0195, c06-math-0196, c06-math-0197.

Figure 6.10 Compensator relative sensitivity function c06-math-0235 (in %) at c06-math-0236 and c06-math-0237 (direct form).

Figure 6.11 Bode plots of c06-math-0238 and c06-math-0239, c06-math-0240.

Figure 6.12 Compensator relative sensitivity function c06-math-0273 (in %) at (a) c06-math-0274 and (b) c06-math-0275 (cascade form).

Figure 6.13 Bode plots of c06-math-0276 and c06-math-0277, c06-math-0278.

Figure 6.14 Parallel PID realization after coefficient scaling and quantization.

Figure 6.17 Digital error calculation from the A/D output for a c06-math-0380-bit A/D converter.

Figure 6.18 Digitized error signal during a 0 A c06-math-0412 5 A c06-math-0413 0 A step-up/step-down load transient.

Figure 6.19 Proportional, integral, and derivative terms during a 0 A c06-math-0415 5 A c06-math-0416 0 A step-up/step-down load transient.

Figure 6.20 Fixed-point implementation of the parallel structure of the PID compensator.

Figure 6.15 Direct PID realization after coefficient scaling and quantization.

Figure 6.22 Direct implementation: signals c06-math-0527, c06-math-0528, and c06-math-0529 during a 0 A c06-math-0530 5 A c06-math-0531 0 A step-up/step-down load transient.

Figure 6.23 Fixed-point implementation of the direct structure.

Figure 6.16 Cascade PID realization after coefficient scaling and quantization.

Figure 6.24 Cascade implementation: signals c06-math-0580, c06-math-0581, and c06-math-0582 during a 0 A c06-math-0583 5 A c06-math-0584 0 A step-up/step-down load transient.

Figure 6.25 Fixed-point implementation of the cascade structure.

Figure 6.26 Comparison between linear and quantized closed-loop response to a 0 A c06-math-0613 5 A step load.

Figure 6.27 Separation between combinational and sequential portions of the controller.

Chapter 7: Digital Autotuning

Figure 7.1 (top) Programmable PID in parallel form and (bottom) block diagram symbol.

Figure 7.2 Bode plots of a PID transfer function under a change in the proportional gain.

Figure 7.3 Bode plots of a PID transfer function under a change in the derivative gain.

Figure 7.4 (top) Programmable PID in the cascade form and (bottom) block diagram symbol.

Figure 7.5 (top) Programmable PID in hybrid form and (bottom) block diagram symbol.

Figure 7.6 A block diagram of an autotuning approach based on injection of a digital perturbation.

Figure 7.7 Phasor diagram (a) during the tuning process, (b) with zero error for the phase margin, (c) with zero error for the crossover frequency, and (d) after the tuning target has been reached.

Figure 7.8 Decomposition of the tuning error c07-math-0118 into a component c07-math-0119 parallel to c07-math-0120 and an orthogonal component c07-math-0121.

Figure 7.9 A block diagram of the PD autotuning approach.

Figure 7.10 Bode plots of c07-math-0207 for different values of c07-math-0208.

Figure 7.11 Loop gain Bode plots before and after the tuning process, first simulation scenario.

Figure 7.12 Closed-loop response to a 0 Ac07-math-02365 A step load before and after the tuning process, first simulation scenario.

Figure 7.13 Proportional, integral, and derivative PID gains during the tuning process, first simulation scenario.

Figure 7.14 Output voltage and inductor current at the onset of the tuning process, first simulation scenario.

Figure 7.15 Evolution of c07-math-0237 and c07-math-0238 during the tuning process, first simulation scenario.

Figure 7.16 Proportional, integral, and derivative PID gains during the tuning process, second simulation scenario.

Figure 7.17 Loop gain Bode plots before and after the tuning process, second simulation scenario.

Figure 7.18 Closed-loop response to a 0 Ac07-math-02475 A step load before and after the tuning process, second simulation scenario.

Figure 7.19 Determination of the autotuning loop gains.

Figure 7.20 Small-signal block diagram of the autotuning loop.

Figure 7.21 A block diagram of the nonlinear relationship between c07-math-0318 and c07-math-0319.

Figure 7.22 Bode diagrams of the crossover frequency and phase margin tuning loop gains.

Figure 7.23 Block diagram of a feedback loop with a digital relay.

Figure 7.24 Feedback loop configuration during the tuning phases.

Figure 7.25 Flowchart for the binary search of c07-math-0428.

Figure 7.26 Output voltage and inductor current during the tuning process.

Figure 7.29 Bode plots of the linear loop gain c07-math-0460 at various steps of the tuning process.

Appendix A: Discrete-Time Linear Systems and the Z-Transform

Figure A.1 Example of (a) convergent and (b) nonconvergent modes associated with real roots of the characteristic equation.

Figure A.2 Example of modes associated with complex roots of the characteristic equation.

Appendix B: Fixed-Point Arithmetic and HDL Coding

Figure B.1 Circular representation of a 3-bit B2C arithmetic system.

Figure B.2 Signal notation of a B2C word b02-math-0106.

Figure B.3 Sign extension b02-math-0124.

Figure B.4 One-bit LSB extension b02-math-0149.

Figure B.5 One-bit LSB truncation b02-math-0180.

Figure B.6 One-bit MSB truncation b02-math-0186.

Figure B.7 Block diagram symbols for addition and multiplication.

Figure B.8 Block diagram symbols for saturated addition and saturated multiplication.

Appendic C: Small-Signal Phase Lag of Uniformly Sampled Pulse Width Modulators

Figure C.1 Waveforms of a TE-USPWM for bapp03-math-0022, bapp03-math-0023.

Figure C.2 Decomposition of a symmetrical modulation into trailing-edge modulations.

List of Tables

Chapter 1: Continuous-Time Averaged Modeling of DC–DC Converters

Table 1.1 Ideal Voltage Conversion Ratios of Basic Converters in CCM

Table 1.2 Synchronous Buck Example Parameters

Table 1.3 Boost Converter Example Parameters

Chapter 2: The Digital Control Loop

Table 2.1 Small-Signal Frequency Responses of Uniformly Sampled Pulse Width Modulators

Chapter 3: Discrete-Time Modeling

Table 3.1 Discrete-Time Small-Signal Model—Trailing-Edge Modulation

Table 3.2 Discrete-Time Small-Signal Model—Leading-Edge Modulation

Table 3.3 Discrete-Time Small-Signal Model—Symmetrical Modulation

Table 3.4 Expressions of c03-math-0429 for Three Different c03-math-0430's. c03-math-0431, c03-math-0432, c03-math-0433

Chapter 4: Digital Control

Table 4.1 Boost PFC Example Parameters

Chapter 6: Compensator Implementation

Table 6.1 c06-math-0037-Domain to c06-math-0038-Domain Conversion Equations

IEEE Press

445 Hoes Lane

Piscataway, NJ 08854

IEEE Press Editorial Board

Tariq Samad, Editor in Chief

George W. Arnold | Vladimir Lumelsky | Linda Shafer
Dmitry Goldgof | Pui-In Mak | Zidong Wang
Ekram Hossain | Jeffrey Nanzer | MengChu Zhou
Mary Lanzerotti | Ray Perez | George Zobrist

Kenneth Moore, Director of IEEE Book and Information Services (BIS)

Technical Reviewers

Francisco J. Azcondo, Universidad de Cantabria

Fujio Kurokawa, Nagasaki University

Jian Sun, Rensselaer Polytechnic Institute

Digital Control of High-Frequency Switched-Mode Power Converters

LUCA CORRADINI
DRAGAN MAKSIMOVIĆ
PAOLO MATTAVELLI
REGAN ZANE

Copyright © 2015 by The Institute of Electrical and Electronics Engineers, Inc.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved

Published simultaneously in Canada

No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission.

Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages.

For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002.

Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com.

Library of Congress Cataloging-in-Publication Data:

Corradini, Luca.

Digital control of high-frequency switched-mode power converters / Luca Corradini, Dragan Maksimovic, Paolo Mattavelli, Regan Zane.

pages cm

Includes bibliographical references and index.

ISBN 978-1-118-93510-1 (cloth)

1. Electric current converters–Automatic control. 2. Switching power supplies–Automatic control. 3. Digital control systems. I. Maksimovic, Dragan, 1961- II. Mattavelli, Paolo. III. Zane, Regan. IV. Title.

TK2796.C67 2015

621.381′044–dc23

2014033408

Preface

Power electronics fundamentals have been established within the framework of continuous-time analysis, averaged modeling of switched-mode power converters, and analog control theory [1-5]. Ever more often, control and management functions around power converters are implemented digitally, expanding the field of fundamentals to discrete-time modeling and digital control concepts specific to power electronics. Standard textbooks and courses dedicated to digital control of dynamic systems in general provide the necessary background but seldom, if ever, address the specifics necessary to fully understand and successfully practice the design of digitally controlled power converters. We attempt, in this book, to fill the gap by treating the fundamental aspects of digital control of high-frequency switched-mode power converters in a systematic and rigorous manner. Our objectives are to put the reader in the position to understand, analyze, model, design, and implement digital feedback loops around power converters, from system-level transfer function formulations to coding practical designs in one of the mainstream hardware description languages (HDLs) such as VHDL or Verilog.

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!

Lesen Sie weiter in der vollständigen Ausgabe!